1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and more particularly, to a semiconductor integrated circuit including a sense amplifier (hereinafter abbreviated as “SA”) that operates when multiple bits of memory cells connected to a single word line (W line) are simultaneously read out.
2. Description of Related Art
Japanese Unexamined Patent Application Publication Nos. 2003-272390 (Honda), 2007-157283 (Shimada), and 08-095686 (Toma) disclose operation of SAs in the case where multiple cells connected to a single W line are simultaneously read out. Honda discloses a configuration in which cells are divided into a plurality of groups to form a plurality of SA groups. The SA groups start to operate at different timings, instead of starting to operate at the same time, thereby reducing a peak current occurring during the operation of the SAs. In addition, according to a technique disclosed by Shimada, SAs are divided into a plurality of SA groups, and the operation timings of the SA groups are shifted from each other in synchronization with a clock. This results in a decrease in peak current occurring during the operation of the SAs.
Meanwhile, as a method for reducing an output circuit current itself, there is known a technique for inverting output data to be transmitted to a communication counterpart (receiving side) according to an interface at the receiving side. As a technique for transmitting one of a signal having a level of “H” and a signal having a level of “L” with higher priority in the data transmission, there is known a technique for terminating a terminal at a transmitting side.
In this regard, in the case of data transmission when a bus (output terminal) is pulled up to the “H” level, for example, the “inversion” of the output data requires less operating current as the number of bits having a logical value “1” is increased in the data to be transmitted. Accordingly, when the number of bits having a logical value “0” is greater than the number of bits having the logical value “1” in the data, the data is transmitted after the logical value thereof is inverted to “1”. During that time, <flag data: 1 bit> indicating that the data is inverted is transmitted at the same time to notify the receiving side of the transmission of the inverted data. Thus, one terminal for transmitting the flag data needs to be provided on the transmitting device side. One such technique is disclosed by Toma.
Furthermore, as a technique of data inversion, Japanese Unexamined Patent Application Publication No. 09-251336 (Takashima) discloses a technique for performing data inversion by dividing data to be transmitted. Japanese Unexamined Patent Application Publication No. 2004-133961 (Yoshida et al.) discloses a technique in which data of a given cycle is compared with output data of the previous cycle and when multiple bits are inverted among all the bits, the data of the given cycle is inverted to be output.
In the related art, as a method for reducing an operating current at the time of reading out multiple bits at the same time, there are known techniques for reducing the operating current in the individual circuits or operations, such as a technique for dividing SAs into groups to be operated and a technique of data inversion. However, there is no prior art technique for reducing an operating current throughout a read operation.
For example, in the case where multiple cells connected to a selected W line are read out at the same time, namely in the case where multiple bits are transmitted from an output terminal at the same time, it has not been known how SAs are divided into groups to be operated and how data transmitted from the SAs which are divided into groups to be operated are subjected to data inversion processing. Moreover, it has not been known the overall optimal configuration.